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1 ? isl6227 dual mobile-friendly pwm controller with ddr option the isl6227 dual pwm controller delivers high efficiency precision voltage regulation from two synchronous buck dc/dc converters. it was designed especially to provide power regulation for ddr memory, chipsets, graphics and other system electronics in notebook pcs. the isl6227?s wide input voltage range capability allows for voltage conversion directly from ac/dc adaptor or li-ion battery pack. automatic mode transition of constant-frequency synchronous rectification at heavy load, and hysteretic (hys) diode-emulation at light load, assure high efficiency over a wide range of conditions. the hys mode of operation can be disabled separately on each pwm converter if constant-frequency continuous-conduction operation is desired for all load levels. efficiency is further enhanced by using the lower mosfet r ds(on) as the current sense element. voltage-feed-forward ramp modulation, current mode control, and internal feedba ck compensation provide fast response to input voltage and load transients. input current ripple is minimized by channel-to-channel pwm phase shift of 0, 90 or 180 (determined by input voltage and status of the ddr pin). the isl6227 can control two independent output voltages adjustable from 0.9v to 5.5v, or by activating the ddr pin, transform into a complete ddr memory power supply solution. in ddr mode, ch2 output voltage vtt tracks ch1 output voltage vddq. ch2 output can both source and sink current, an essential power supply feature for ddr memory. the reference voltage vref required by ddr memory is generated as well. in dual power supply applications the isl6227 monitors the output voltage of both ch1 and ch2. an independent pgood (power good) signal is asserted for each channel after the soft-start sequence has complet ed, and the output voltage is within pgood window. in ddr m ode ch1 generates the only pgood signal. built-in overvoltage protection prevents the output from going above 115% of the set point by holding the lower mosfet on and the upper mosfet off. when the output voltage re-enters regulation, pgood will go high and normal operation automatically resumes. once the soft-start sequence has completed, undervoltage protection latches the offending channel off if the output drops below 75% of its set point value. adjustable overcurrent protection (ocp) monitors the voltage drop across the r ds(on) of the lower mosfet. if more precise current-sensing is required, an ex ternal current sense resistor may be used. features ? provides regulated output voltage in the range 0.9v to 5.5v ? operates from an input battery voltage range of 5v to 28v or from 3.3v/5v system rail ? complete ddr1 and ddr2 memory power solution with vtt tracking vddq/2 and a vddq/2 buffered reference output ? flexible pwm or hys plus pwm mode selection with hys diode emulation at light loads for higher system efficiency ?r ds(on) current sensing ? excellent dynamic response with voltage feed-forward and current mode control accommodating wide range lc filter selections ? undervoltage lock-out on vcc pin ? power-good, overcurrent, overvoltage, undervoltage protection for both channels ? synchronized 300khz pwm operation in pwm mode ? pb-free available (rohs compliant) applications ? notebook pcs and desknotes ? tablet pcs/slates ? hand-held portable instruments ordering information part number part marking temp. range (c) package pkg. dwg. # isl6227ca* isl 6227ca -10 to +100 28 ld qsop m28.15 isl6227caz* (note) isl 6227caz -10 to +100 28 ld qsop (pb-free) m28.15 isl6227ia* isl 6227ia -40 to +100 28 ld qsop m28.15 isl6227iaz* (note) isl 6227iaz -40 to +100 28 ld qsop (pb-free) m28.15 isl6227hrz* (note) isl 6227hrz -10 to +100 28 ld qfn (pb-free) l28.5x5 isl6227irz* (note) isl 6227irz -40 to +100 28 ld qfn (pb-free) l28.5x5 *add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004-2007, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. may 4, 2009 data sheet fn9094.7
2 fn9094.7 may 4, 2009 generic application circuits pinouts isl6227 28 ld qsop top view isl6227 28 ld 5x5 qfn top view en1 gnd ddr vsen1 vin pg1 vcc vout1 isen1 lgate1 pgnd1 boot1 ugate1 phase1 isen2 lgate2 pgnd2 boot2 ugate2 phase2 en2 vsen2 vout2 ocset2 ocset1 soft1 soft2 pg2/ref 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 ugate2 boot2 isen2 en2 vout2 vsen2 ocset2 phase1 ugate1 boot1 isen1 en1 vout1 vsen1 ocset1 soft1 ddr vin pg1 pg2/ref soft2 pgn1 lgate1 gnd vcc lgate2 pgnd2 phase2 gnd 29 v in v out1 v out2 +1.80v +1.20v +5v to +28v l1 q1 q2 ocset1 ddr isl6227 application circuit for two channel power supply pwm1 pwm2 l2 q3 q4 c2 ocset2 vcc en2 en1 +5v + c1 + isl6227 application circuit for complete ddr memory power supply v in vddq vtt +2.50v +1.25v +5v to 28v l1 q1 q2 ocset1 ddr pwm1 pwm2 l2 q3 q4 ocset2 vcc en2 en1 +5v vref +1.25v pg2/vref c1 + c2 + isl6227
3 fn9094.7 may 4, 2009 absolute m aximum ratings bias voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +6.5v input voltage, v in . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +28.0v phase, ugate . . . . . . . . . . . . . . . . . . . gnd -5v (note 1) to 33.0v boot, isen . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to +33.0v boot with respect to phase . . . . . . . . . . . . . . . . . . . . . . . . + 6.5v all other pins . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v cc + 0.3v recommended operating conditions bias voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0v 5% input voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . .+5.0v to +28.0v ambient temperature range . . . . . . . . . . . . . . . . . -10c to +100c junction temperature range . . . . . . . . . . . . . . . . . -10c to +125c thermal information thermal resistance (typical) ja (c/w) jc (c/w) qsop package (note 2) . . . . . . . . . . . . . 80 n/a qfn package (notes 3, 4) . . . . . . . . . . . . 36 6 maximum junction temperature (plastic package). . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. 250ns transient. see confining the negative phase no de voltage swing in application information section 2. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 fo r details. 3. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 5. limits established by characteri zation and are not production tested. electrical specifications recommended operating conditions, unless otherwise noted. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. parameter symbol test conditions min typ max units vcc supply bias current i cc lgatex, ugatex open, vsenx forced above regulation point, v in > 5v -1.83.0ma shut-down current i ccsn --1a vcc uvlo rising vcc threshold v ccu 4.3 4.45 4.5 v falling vcc threshold v ccd 44.144.34v v in input voltage pin current (sink) i vin --35a shut-down current i vins --1a oscillator pwm1 oscillator frequency f c commercial, isl6227c 255 300 345 khz industrial, isl6227i 240 300 345 khz ramp amplitude, pk-pk v r1 v in = 16v (note 5) - 2 - v ramp amplitude, pk-pk v r2 v in = 5v (note 5) - 0.625 - v ramp offset v roff (note 5) - 1 - v ramp/v in gain g rb1 v in 4.2v (note 5) - 125 - mv/v ramp/v in gain g rb2 v in 4.1v (note 5) - 250 - mv/v reference and soft-start internal reference voltage v ref -0.9- v reference voltage accuracy -1.0 - +1.0 % isl6227
4 fn9094.7 may 4, 2009 soft-start current during start-up i soft --4.5- a soft-start complete threshold v st (note 5) - 1.5 - v pwm converters load regulation 0.0ma < i vout1 < 5.0a; 5.0v < v batt < 28.0v -2.0 - +2.0 % vsen pin bias current i vsen (note 5) - 80 - na minimum duty cycle d min -4-% maximum duty cycle d max -87- % vout pin input impedance i vout vout = 5v - 134 - k undervoltage shut-down level v uvl fraction of the set point; ~2s noise filter 70 75 80 % overvoltage protection v ovp1 fraction of the set point; ~2s noise filter 110 115 - % gate drivers upper drive pull-up resistance r 2ugpup v cc = 5v - 4 8 upper drive pull-down resistance r 2ugpdn v cc = 5v - 2.3 4 lower drive pull-up resistance r 2lgpup v cc = 5v - 4 8 lower drive pull-down resistance r 2lgpdn v cc = 5v - 1.1 3 power good and control functions power good lower threshold v pg- fraction of the set point; ~3s noise filter 84 89 92 % power good higher threshold v pg+ fraction of the set point; ~3s noise filter. 110 115 120 % pgoodx leakage current i pglkg v pullup = 5.5v - - 1 a pgoodx voltage low v pgood i pgood = -4ma - 0.5 1 v isen sourcing current (note 5) - - 260 a ocset sourcing current range 2-20a en - low (off) --0.8v en - high (on) 2.0 - - v continuous-conduction-mode(ccm) enforced (hys operation inhibited) voutx pulled low - - 0.1 v automatic ccm/hys operation enabled voutx connected to the output 0.9 - - v ddr - low (off) --0.8v ddr - high (on) 3- -v ddr ref output voltage v ddref ddr = 1, i ref = 0...10ma 0.99* v oc2 v oc2 1.01* v oc2 v ddr ref output current i ddref ddr = 1 (note 5) - 10 12 ma electrical specifications recommended operating conditions, unless otherwise noted. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter symbol test conditions min typ max units isl6227
5 fn9094.7 may 4, 2009 typical operation performance figure 1. efficiency of channel 1, 2.5v, hys/pwm mode figure 2. efficiency of channel 2, 1.8v, hys/pwm mode figure 3. output voltage of channel 1 vs load fi gure 4. output voltage of channel 2 vs load figure 5. switching frequency over-temper ature figure 6. reference voltage accuracy over-temperature 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.00 10.0 load current (a) efficiency (%) eff@ 5v eff@ 12v eff@ 19.5v eff@ 5v, pwm eff@ 12v, pwm eff@ 19.5v, pwm 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.00 10.0 load current (a) efficiency (%) eff@ 19.5v eff@ 19.5v, pwm eff@ 12v, pwm eff@ 5v eff@ 5v, pwm eff@ 12v 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 012345 output voltage (v) load current (a) v out @ 19.5v v out @ 12v v out @ 19.5v, pwm v out @ 5v v out @ 5v, pwm v out @ 12v, pwm 1.78 1.79 1.80 1.81 1.82 1.83 012345 output voltage (v) load current (a) v out @ 19.5v v out @ 12v v out @ 12v, pwm v out @ 5v v out @ 5v, pwm v out @ 19.5v, pwm 286 288 290 292 294 296 298 300 302 304 306 308 -20 0 20 40 60 80 100 120 temperature (c) frequency (khz) 75% quantile 25% quantile frequency mean 0.8975 0.8980 0.8985 0.8990 0.8995 0.9000 0.9005 0.9010 0.9015 0.9020 0.9025 -20 0 20 40 60 80 100 120 temperature (c) vref (v) 75% quantile 25% quantile vref mean isl6227
6 fn9094.7 may 4, 2009 figure 7. load transient (0a to 3a at channel 1) (diode emulation mode) figure 8. load transient (0a to 3a at channel 1) (forced pwm mode) figure 9. load transient (0a to 2a at channel 2) (diode emulation mode) figure 10. load transient (0a to 3a at channel 2) (forced pwm mode) figure 11. input step-up transient at pwm mode figure 12. input step-up transient at hys mode typical operation performance (continued) vo1 vphase1 ilo1 vo2 vo1 vphase1 ilo1 vo2 vo1 ilo1 vo2 vphase1 vo1 vphase1 ilo1 vo2 vo1 vphase2 ilo2 vo2 vo1 vphase2 ilo2 vo2 vo1 ilo2 vo2 vphase2 vo1 vphase2 ilo2 vo2 vin1 vo1 vo2 vin1 vo1 vo2 vin1 vo1 vo2 vin1 vo1 vo2 isl6227
7 fn9094.7 may 4, 2009 figure 13. input step-down transient at pwm mode figure 14. input step-down transient at hys mode figure 15. soft-start interval at zero initial voltage of vo figure 16. soft-start interv al with non-zero initial voltage of vo figure 17. operation at light load of 100ma, channel 1 figure 18. operation at heavy load of 4a, channel 1 typical operation performance (continued) vin1 vo1 vo2 vin1 vo1 vo2 vin1 vo1 vo2 vin1 vo1 vo2 en1 pg1 soft1 vo1 en1 pg1 soft1 vo1 en1 pg1 soft1 vo1 en1 pg1 soft1 vo1 vo1 vphase1 ilo1 vo2 vo1 vphase1 ilo1 vo2 vo1 vphase1 ilo1 vo2 vo1 vphase1 ilo1 vo2 isl6227
8 fn9094.7 may 4, 2009 figure 19. overcurrent protection at channel 1 figure 20. short-circuit protection at channel 1 figure 21. mode transition of hys _ pwm figure 22. mode transition of pwm hys figure 23. normal shutdown, i out = 1.5a figure 24. v cc power-up in ddr mode typical operation performance (continued) vo1 pg1 ilo1 vo2 vo1 pg1 ilo1 vo2 vo1 pg1 ilo1 vo2 vo1 pg1 ilo1 vo2 vo1 vphase1 ilo1 vo2 vo1 vphase1 ilo1 vo2 vo1 vphase2 ilo2 vo2 vo1 vphase2 ilo2 vo2 en1 pg1 soft1 vo1 en1 pg1 soft1 vo1 vtt ocset vddq vcc vtt ocset vddq vcc isl6227
9 fn9094.7 may 4, 2009 figure 25. vin = 19v, vddq 3a step load, vtt 0a load fi gure 26. vin = 19v, vddq 3a step load, vtt 3a load figure 27. vin = 19v, load step on vtt, vddq hys mode, 0.14a figure 28. vin = 19v, load step on vtt, vddq pwm mode, 0.14a figure 29. input line transient in ddr mode figure 30. vtt follows vddq, enable 2 is high typical operation performance (continued) vddq vtt il1 pgood1 vddq pgood1 vtt il1 vddq vtt il1 pgood1 vddq pgood1 vtt il1 vddq vtt il2 ocset2 vddq vtt ocset2 il2 vddq vtt il2 ocset2 vddq vtt ocset2 il2 vddq vin vtt ocset2 vddq vin vtt ocset2 vddq en1 vtt il1 vtt en1 vddq il1 isl6227
10 fn9094.7 may 4, 2009 functional pin description gnd signal ground for the ic. lgate1, lgate2 these are the outputs of the lower mosfet drivers. pgnd1, pgnd2 these pins provide the return connection for lower gate drivers, and are connected to sources of the lower mosfets of their respective converters. phase1, phase2 the phase1 and phase2 points are the junction points of the upper mosfet sources, output filter inductors, and lower mosfet drains. connect these pins to the respective converter?s upper mosfet source. ugate1, ugate2 these pins provide the gate drive for the upper mosfets. boot1, boot2 these pins power the upper mosfet drivers of the pwm converter. connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. the anode of the bootstrap diode is connected to the vcc voltage. isen1, isen2 these pins are used to monitor the voltage drop across the lower mosfet for current feedback and overcurrent protection. for precise current detection these inputs can be connected to the optional current sense resistors placed in series with the source of the lower mosfets. en1, en2 these pins enable operation of the respective converter when high. when both pins are low, the chip is disabled and only low leakage current is taken from vcc and vin. en1 and en2 can be used independently to enable either channel 1 or channel 2. vout1, vout2 these pins, when connected to the converter?s respective outputs, set the converter operat ing in a mixed hysteretic mode or pwm mode, depending on the load conditions. it also provides the voltage to the chip to clamp the pwm error amplifier in hysteretic mode to achieve smooth hys/pwm transition. when connected to ground, these pins command forced continuous conduction mode (pwm) at all load levels. vsen1, vsen2 these pins are connected to the resistive dividers that set the desired output voltage. the pgood, uvp, and ovp circuits use this signal to report output voltage status. ocset1 this pin is a buffered 0.9v internal reference voltage. a resistor from this pin to ground sets the overcurrent threshold for the first controller. soft1, soft2 these pins provide soft-start function for their respective controllers. when the chip is enabled, the regulated 4.5a pull-up current source charges the capacitor connected from the pin to ground. the output vo ltage of the converter follows the ramping voltage on the soft pin in the soft-start process with the soft pin vo ltage as reference. when the soft pin voltage is higher than 0.9v, the error amplifier will use the internal 0.9v referenc e to regulate output voltage. in the event of undervoltage and overcurrent shutdown, the soft-start pin is pulled down though a 2k resistor to ground to discharge the soft-start capacitor. ddr when the ddr pin is low, the chip can be used as a dual switcher controller. the output voltage of the two channels can be programmed independently by vsenx pin resistor dividers. the pwm signals of channel 1 and channel 2 will be synchronized 180 out-of-phase. when the ddr pin is high, the chip transforms in to a complete ddr memory solution. the ocset2 pin becomes an input through a resistor divider tracking to vddq/2. the pg2/ref pin becomes the output of the vddq/2 buffered voltage. the vddq/2 voltage is also used as the reference to the error amplifier by the second channel. the channel phase-shift synchronization is determined by the vin pin when ddr = 1 as described in vin below. vin this pin has multiple functions. when connected to battery voltage, it provides battery voltage to the oscillator as a feed-forward for the rejection of input voltage variation. the ramp of the pwm comparator is proportional to the voltage on this pin (see table 1 and table 2 for details). while the ddr pin is high in the ddr application, and when the vin pin voltage is greater than 4.2v when connecting to a battery, it commands 90 out-of-phase channel synchronization, with the second channel lagging the first channel, to reduce inter-channel interference. when the pin voltage is less than 4.2v, this pin commands in-phase channel synchronization. pg1 pgood1 is an open drain output used to indicate the status of the output voltage. this pin is pulled low when the first channel output is out of -11% to +15% of the set value. isl6227
11 fn9094.7 may 4, 2009 pg2/ref this pin has a double function, depending on the mode of operation. when the chip is used as a dual channel pwm controller (ddr = 0), the pin provides an open drain pgood2 function for the second channel the same way as pg1. the pin is pulled low when the second channel output is out of -11% to +15% of the set value. in ddr mode (ddr = 1), this pin is the output of the buffer amplifier that takes vddq/2 voltage applied to ocset2 pin from the resister divider. it can source a typical 10ma current. ocset2 in a dual channel application with ddr = 0, a resistor from this pin to ground sets the overcurrent threshold for the second channel controller. its voltage is the buffered internal 0.9v reference. in the ddr application with ddr = 1, this pin connects to the center point of a resistor divi der tracking the vddq/2. this voltage is then buffered by an amplifier voltage follower and sent to the pg2/ref pin. it sets the reference voltage of channel 2 for its regulation. vcc this pin powers the controller. typical application figures 31 and 32 show the application circuits of a dual channel dc/dc converter for a notebook pc. the power supply in figure 31 provides +2.5v and +1.8v voltages for memory and the graphics interface chipset from a +5.0vdc to a 28vdc battery voltage. figure 32 illustrates the application circuit for a ddr memory power solution. the power supply shown in figure 32 generates +2.5v vddq voltage from a battery. the +1.25v vtt termination voltage tracks vddq/2 and is derived from +2.5v vddq. to complete the ddr memory power requirements, the +1.25v refe rence voltage is provided through the pg2 pin. isl6227
12 fn9094.7 may 4, 2009 figure 31. typical application circuit as dual switcher, vout1 = 2.5v, vout = 1.8v rs1 2.0k rs2 2.0k q1 lo1 co12 4.7 f cin1 10 f cdc d2 bat54w rbt1 cbt1 cbt2 rbt2 lo2 q2 cin2 10f co21 220 f co22 4.7 f rset1 100k csoft1 0.01 f rfb12 10k cfb1 0.01 f soft1 pg1 ocset1 en1 vout1 vsen1 pgnd1 lgate1 isen1 phase1 ugate1 boot1 gnd vcc vin pgnd2 lgate2 isen2 phase2 ugate2 boot2 vout2 pg2 soft2 v1 (2.5v) v2 (1.8v) ddr 220 f en2 vcc (5v) u1 fds6912a fds6912a q1 4.7h cin1 10 f cdc 4.7f d1 bat54w 0 cb 0.15f cbt2 0.15f lo2 q2 cin2 co21 csoft1 0.01 f rfb11 17.8k rfb12 10k v in v co11 220 f vcc (5v) u1 fds6912a fds6912a isl6227 ocset2 vsen2 rfb21 10k rfb22 10k cfb2 csoft2 0.01f rset2 100k 0.01 f 4.7h 0 rs1 rs2 1.0k q1 lo1 4.6 h co11 4.7 f cin1 10 f cdc 4.7 f rbt1 cbt1 0.15f cbt2 rbt2 lo2 1.5 q2 220f co22 4.7f rset1 100k csoft1 0.01f rfb1 rfb12 10k cfb1 0.01 f soft1 pg1 ocset1 en1 vout1 vsen1 pgnd1 lgate1 isen1 phase1 ugate1 boot1 gnd vcc vin ocset2_vddq/2 pg2_ref pgnd2 lgate2 isen2 phase2 ugate2 boot2 vsen2 vout2 soft2 vin vref 10k vddq vddq/2 rd2 10k cf 0.1 vddq (2.5v) vtt (1.25v) ddr co13 220 f en2 vcc (5v) csoft2 (n/u) u1 fds6912a fds6912a rs1 2.0k q1 lo1 4.6 h co11 4.7 f cin1 10 f cdc 4.7 f d1 bat54w d2 bat54w 0 0.15f 0 1.5h q2 cin2 4.7f co21 rfb1 17.8k rfb12 cfb1 0.01 f vcc vin pg2_ref pgnd2 lgate2 vsen2 vout2 soft2 vin (vddq/2) rd1 cf 0.1f vddq (2.5v) cref 4.7f ddr co13 220 f en2 vcc (5v) 0.01f u1 fds6912a isl6227 figure 32. typical application as ddr memory power supply, vddq = 2.5v, vtt = 1.25v vddq isl6227
13 fn9094.7 may 4, 2009 block diagram error amp 1 v hys = 15mv vsen1 hysteretic comparator 1 mode change comp 1 300k pwm1 + 0.9v isen1 140 sample current sample current phase1 pgnd1 ugate1 boot1 lgate1 vcc 0.9v reference ocset1 1/2.9 ocset1 1/33.1 isen1 error amp 2 adaptive dead-time v hys = 15mv vsen2 hysteretic comparator 2 mode change comp 2 1m 15pf 1.25pf 500k 300k pwm2 + 0.9v isen2 140 sample current sample current phase2 pgnd2 ugate2 boot2 lgate2 vcc diode emulation v/i sample timing + 0.9v reference ocset2 1/2.9 ocset2 1/33.1 isen2 ddr vin vcc duty cycle ramp generator pwm channel phase control oc2 oc1 ddr = 0 ddr = 1 ddr vtt ddr = 0 ddr = 1 8 clock cycles same state for required to latch overcurrent fault 8 clock cycles same state for required to change pwm or hys mode 8 clock cycles same state for required to change pwm or hys mode 8 clock cycles same state for required to latch overcurrent fault vcc pg1 reference ov uv pgood ddr vref buffer amp ddr = 1 ddr = 0 1.25pf 500k 1m 15pf ov uv pgood vout1 vout2 pwm/hys transition adaptive dead-time diode emulation v/i sample timing pwm/hys transition volts/sec clamp volts/sec clamp oc1 ddr por fault latch bias supplies reference enable soft-start gnd en1 en2 ref/pg2 soft1 soft2 ddr mode control oc2 ref ref (200k , ddr = 1) 4.4k 4.4k ddr en1 en2 vin ch1/ch2 011 0v ? 28.0v 180 111 4.2 < vin < 28.0v vin < 4.2 90 0 isl6227
14 fn9094.7 may 4, 2009 theory of operation operation the isl6227 is a dual channel pwm controller intended for use in power supplies for graphic chipsets, sdram, ddr dram, or other low voltage power applications in modern notebook and sub-notebook pcs. the ic integrates two control circuits for two synchronous buck converters. the output voltage of each controller can be set in the range of 0.9v to 5.5v by an external resistive divider. the synchronous buck converters can operate from either an unregulated dc source, such as a notebook battery, with a voltage ranging from 5.0v to 28v, or from a regulated system rail of 3.3v or 5v. in either operational mode the controller is biased from the +5v source. the controllers operate in the current mode with input voltage feed-forward which simplifies feedback loop compensation and rejects input voltage variation. an integrated feedback loop compensation dramatically reduces the number of external components. depending on the load level, c onverters can operate either in a fixed 300khz frequency mode or in a hys mode. switch-over to the hys mode of operation at light loads improves converter efficiency and prolongs battery life. the hys mode of operation can be inhibited independently for each channel if a variable frequency operation is not desired. the isl6227 has a special means to rearrange its internal architecture into a complete ddr solution. when the ddr pin is set high, the second channel can provide the capability to track the output voltage of the first channel. the buffered reference voltage required by ddr memory chips is also provided. initialization the isl6227 initializes if at least one of the enable pins is set high. the power-on reset (por) function continually monitors the bias supply voltage on the vcc pin, and initiates soft-start operation when en1 or en2 is high after the input supply voltage exceeds 4.45v. should this voltage drop lower than 4.14v, the por disables the chip. soft-start when soft-start is initiated, the voltage on the soft pin of the enabled channel starts to ramp up gradually with the internal 4.5a current charging the soft-start capacitor. the output voltage follows the soft-start voltage with the converter operating at 300khz pwm switching frequency. when the soft pin voltage reaches 0.9v, the output voltage comes into regulation, (see block diagram). when the soft voltage reaches 1.5v, the power good (pgood) and the mode control is enabled. the soft-start process is depicted in figure 33. even though the soft-start pin voltage continues to rise after reaching 1.5v, this voltage do es not affect the output voltage. during the soft-start, the converter always operates in continuous conduction mode independent of the load level or vout pin connection. the soft-start time (the time from the moment when en becomes high to the moment when pgood is reported) is determined by equation 1: the time it takes the output voltage to come into regulation can be obtained from equation 2: during soft-start stage before the pgood pin is ready, the undervoltage protection is prohi bited. the overvoltage and overcurrent protection functions are enabled. if the output capacitor has residue voltage before startup, both lower and upper mosfets are in off-state until the soft-start capacitor charges equal the vsen pin voltage. this will ensure the output voltage starts from its existing voltage level. ch3 1.0v ch2 2.0v ch4 5.0v m1.00ms ch1 5.0v 3 2 4 1 en 0.9v 1.5v sof t vout pgood figure 33. start-up t soft 1.5v csoft 4.5 a ---------------------------------- = (eq. 1) t rise 0.6 t soft = (eq. 2) isl6227
15 fn9094.7 may 4, 2009 output voltage program the output voltage of either channel is set by a resistive divider from the output to ground. the center point of the divider is connected to the vsen pin as shown in figure 34. the output voltage value is determined by equation 3: where 0.9v is the value of the internal reference. the vsen pin voltage is also used by the controller for the power good function and to detect undervoltage and overvoltage conditions. operation mode control voutx pin programs the two channels of isl6227 in two different operational modes: 1. if voutx is connected to ground, the channel will be put into a fixed switching frequency of 300khz ccm, also known as forced pwm mode regardless of load conditions. 2. if the voutx is connected to the output voltage, the channel will operate in either fixed 300khz pwm mode or hys mode, depending on the load conditions. it operates in the pwm mode when the load current exceeds the critical discontinuous conduction value, otherwise it will operate in a hys mode, as shown in the following table. the two channels can be programmed to operate in different modes depending on the voutx connection and the load current. once both channels operate in the pwm mode, however, they will be synchronized to the 300khz switching clock. the 180 phase shift reduces the noise couplings between the two channels and reduces the input current ripple. the critical discontinuous conduction current value for the pwm to hys mode switch-over can be calculated by equation 4: the hys mode to pwm switch-over current i hys1 is determined by the activation time of the hys mode controller. it is affected by the esr, the inductor value, the input and output voltage. the hys mode control can improve converter efficiency with reduced switching frequency. the efficiency is further improved by the diode emulation scheme in discontinuous conduction mode. the diode emulation scheme does not allow the inductor sink current from the output capacitor, thereby reducing the circulating energy. it is achieved by sensing the free-wheeling current going through the synchronous mosfet through phase node voltage polarity change after the upper mosfet is turned off. before the current reverses direction, the lower mosfet gate pulses are terminated. the pwm-hys and hys-pwm sw itch-over is provided automatically by the mode control circuit, which constantly monitors the inductor current through phase voltage polarity, and alters the way the gate driver pulse signal is generated. mode transition for a buck regulator, if the load current is higher than critical value i hys1 , the voltage drop on the synchronous mosfet in the free-wheeling period is always negative, and vice versa. the mode control circuit monitors the phase node voltage in the off-period. the polarity of this voltage is used as the criteria for whether the load current is greater than the critical value, and thus determ ines whether the converter will operate in pwm or hys mode. to prevent chatter between operating modes, the circuit looks for eight sequentially matching polarity signals before it decides to perform a mode change. the algorithm is true for both ccm-hys and hys-ccm transitions. in the hys mode, the pwm comparator and the error amplifier, that provided control in the ccm mode, are put in a clamped stage and the hysteretic comparator is activated. a change is also made to the gate logic. the synchronous mosfet is controlled in diode emulation fashion, hence the current in the synchronous mosfet will be kept in one direction only. figures 35 and 36 illustrate the mode change by counting eight switching cycles. vout pin inductor current operation mode gnd any value forced pwm connects to output voltage i hys hys connects to output voltage >i hys1 pwm v o 0.9v r1 r2 + () ? r2 --------------------------------------------- - = (eq. 3) r2 r1 ugate lgate isl6227 l1 q1 q2 c1 vout vsen v in r cs isen ocset r oc c z v o figure 34. output voltage program i hys v in v o ? () v o ? 2f sw l o v in ? ? ? ---------------------------------------------------- = (eq. 4) isl6227
16 fn9094.7 may 4, 2009 if load current slowly incr eases or decreases, mode transition will occur naturally, as described in figures 35 and 36; however, if there is an instantaneous load current increase resulting in a large output voltage drop before the hysteretic mode controller responds, a comparator with threshold of 20mv below the reference voltage will be tripped, and the chip will jump into the forced pwm mode immediately. the pwm controller will process the load transient smoothly. once the pwm controller is engaged, eight consecutive switching cycles of negative indu ctor current are required to transition back to the hysteretic mode. in this way, chattering between the two modes is prevented. current sinking during the 8 pwm switching cycle dumps energy to input, smoothing output voltage load step-down. as a side effect to this design, the comparator may be triggered consistently if the esr of the capacitor is so big that the output ripple voltage exceeds the 20mv window, resulting in a pure pwm pulse. the pwm error amplifier is put in clamped voltage during the hysteretic mode. the output voltage through the vout pin and the input voltage through the vin pin are used to determine the error amplifier output voltage and the duty cycle. the error amplifier sta ys in an armed state while waiting for the transition to occur. the transition decision point is aligned with the pwm clock. when the need for transition is detected, there is a 500ns delay between the first/last pulse of the pwm cont roller from the last/first pulse of the hysteretic mode controller. current sensing the current on the lower mosfet is sensed by measuring its voltage drop within its on-time. in order to activate the current sampling circuitry, two conditions need to be met. (1) the lgate is high and (2) the phase pin sees a negative voltage for regular buck operation, which means the current is freewheeling through lower mosfet. for the second channel of the ddr application, the phase pin voltage needs to be higher than 0.1v to activa te the current sensing circuit for bidirectional current sensing. the current sampling finishes at about 400ns after the lower mosfet has turned on. this current information is held for current mode control and overcurrent protection. the current sensing pin can source up to 260a. the current sense resistor and ocset resistor can be adjusted simultaneously for the same overcurrent protection level, however, the current sensing gain will be changed only according to the current sense resistor value, which will affect the current feedback loop gain. the middle point of the isen current can be at 75a, but it can be tuned up and down to fit application needs. if another channel is switching at the moment the current sample is finishing, it could cause current sensing error and phase voltage jitter. in the design stage, the duty cycles and synchronization have to be analyzed for all the input voltage and load conditions to reduce the chance of current sensing error. the relationship between the sampled current and mosfet current is given by equation 5: which means the current sensin g pin will source current to make the voltage drop on the mosfet equal to the voltage generated on the sensing resistor, plus the internal resistor, along the isen pin current flowing path. feedback loop compensation both channel pwm controllers have internally compensated error amplifiers. to make internal compensation possible several design measures were taken. ? the ramp signal applied to the pwm comparator has been made proportional to the input voltage by the vin pin. this keeps the product of the modulator gain and the input voltage constant even when the input voltage varies. ? the load current proportional signal is derived from the voltage drop across the lower mosfet during the pwm off time interval, and is subtracted from the error amplifier figure 35. ccm?hysteretic transition figure 36. hysteretic?ccm transition pwm hysteretic 1 2 3 4 5 6 7 8 vou t iind phase opera t ion mode of t t t t comp pwm hysteretic 1 2 3 4 5 6 7 8 vout iind phase comp opera t ion mode of t t t t i sen r cs 140 + () r ds on () i d = (eq. 5) isl6227
17 fn9094.7 may 4, 2009 output signal before the pwm comparator input. this effectively creates an internal current control loop. the resistor connected to the isen pin sets the gain in the current sensing. the following expression estimates the required value of the current sense resistor, depending on the maximum continuous load current, and the value of the mosfets r ds(on) , assuming the isen pin sources 75a current. because the current sensing circuit is a sample-and-hold type, the information obtained at the last moment of the sampling is used. this current sensing circuit samples the inductor current very close to its peak value. the current feedback essentially in jects a resistor r i in series with the original lc filter as show n in figure 37, where the sample-and-hold effect of the current loop has been ignored. vc and vo are small signal components extracted from its dc operation points. the value of the injected resistor can be estimated by equation 7: r i is in k , and r ds and r cs are in . v in divided by v ramp , is defined as gm, which is a constant 8db or 18db for both channels in dual switcher applications, when v in is above 3v. refer to table 1 for the ramp amplitude in different v in pin connections. the feed-forward effect of the v in is reflected in gm. v c is defined as the error amplifier output voltage. the small signal transfer function from the error amplifier output voltage v c to the output voltage v o can be written in equation 8: the dc gain is derived by shorting the inductor and opening the capacitor. there is one zero and two poles in this transfer function. the zero is rela ted to esr and the output capacitor. the first pole is a low frequency pole associated with the output capacitor and its charging resistors. the inductor can be regarded as short. the second pole is the high frequency pole related to the inductor. at high frequency the output capacitor can be regarded as a short circuit. by approximation, the poles and zero are inversely proportional to the time constants, associated with inductor and capacitor, by equations 9, 10 and 11: since the current loop separates the lc resonant poles into two distant poles, and esr zero tends to cancel the high frequency pole, the second order system behaves like a first order system. this control meth od simplifies the design of the internal compensator and makes it possible to accommodate many applications having a wide range of parameters. the schematics for the internal compensator is shown in figure 38. table 1. pwm comparator ramp amplitude for dual switcher application vin pin connections vramp amplitude ch1 and ch2 input voltage input voltage >4.2v vin/8 input voltage <4.2v 1.25v gnd 1.25v r cs i max r ds on () ? 75 a ------------------------------------------ = 140 ? (eq. 6) figure 37. the equivalent circuit of the power stage with current loop included + - gm*vc ri lo dcr co ro vo esr + - r i v in v ramp ---------------- - r ds on () r cs 140 + ---------------------------- 4.4k ? = (eq. 7) table 2. pwm comparator ramp voltage amplitude for ddr application vin pin connection vramp amplitude ch1 input voltage input voltage >4.2v vin/8 input voltage <4.2v 1.25v gnd 1.25v ch2 input voltage >4.2v 0.625v gnd 1.25v gs () g m r o r i dcr r o ++ --------------------------------------- s wz -------- - 1 + ?? ?? s wp1 ------------ - 1 + ?? ?? s wp2 ------------ - 1 + ?? ?? --------------------------------------------------------- = (eq. 8) wz 1 esr*c o ----------------------- - = (eq. 9) wp1 1 esr r i dcr + () r o || + () *c o ------------------------------------------------------------------------------ - = (eq. 10) wp2 r i dcr esr ++ r o || l o ---------------------------------------------------------- = (eq. 11) isl6227
18 fn9094.7 may 4, 2009 its transfer function can be written as equation 12: where: f z1 = 6.98khz, f z2 = 380khz, and f p1 = 137khz outside the isl6227 chip, a capacitor c z can be placed in parallel with the top resistor in the feedback resistor divider, as shown in figure 34. in this case the transfer function from the output voltage to the middle point of the divider can be written as equation 13: the ratio of r 1 and r 2 is determined by the output voltage set point; therefore, the position of the pole and zero frequency in the above equation may not be far apart; however, they can improve t he loop gain and phase margin with the proper design. the c z can bring the high frequency transient output voltage variation directly to the vsen pin to cause the pgood drop. such an effect should be considered in the selection of c z . from the analysis above, the system loop gain can be written as equation 14: figure 39 shows the composition of the system loop gain. as shown in the graph, the power stage becomes a well damped second order system as compared to the lc filter characteristics. the esr zero is so close to the high frequency pole that they cancel each other out. the power stage behaves like a first orde r system. with an internal compensator, the loop gain transfer function has a cross over frequency at about 30khz. with a given set of parameters, includ ing the mosfet r ds(on) , current sense resistor r cs , output lc filter, and voltage feedback network, the system loop gain can be accurately analyzed and modified by the system design ers based on the application requirements. gate control logic the gate control logic transl ates generated pwm signals into gate drive signals providing necessary amplification, level shift, and shoot-through protection. it bears some functions that help to optimi ze the ic performance over a wide range of the operational conditions. as mosfet switching time can vary dramat ically from type to type, and with the input voltage, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower mosfets. dual-step conversion the isl6227 dual channel controller can be used either in power systems with a single-stage power conversion, when the battery power is convert ed into the desired output voltage in one step, or in the systems where some intermediate voltages are initially established. the choice of the approach may be dictated by the overall system design criteria, or the approach may be a matter of voltages available to the system designer, as in the case of pci card applications. when the output voltage is regulated from low voltage such as 5v, the feed-forward ramp may become too shallow, creating the possibility of duty-fact or jitter; this is particularly relevant in a noisy environment. noise susceptibility, when operating from low level regulated power sources, can be improved by connecting the vin pin to ground, by which the feed-forward ramp generator will be internally reconnected from the vin pin to the vcc pin, and the ramp slew rate will be doubled. figure 38. the internal compensator + - 1.25pf 1m 15pf 500k 300k vsen 0.9v to pwm comparator 4.4k vc isen gcomp s () 1.857 10 5 s 2 f z1 -------------- - 1 + ?? ?? s 2 f z2 -------------- - 1 + ?? ?? ? s s 2 f p1 --------------- 1 + ?? ?? -------------------------------------------------------------------------------------------- - = (eq. 12) gfd s () r 2 r 1 r 2 + -------------------- - sr 1 c z 1 + sr 1 r 2 || () c z 1 + --------------------------------------------- - = (eq. 13) gloop s () gs () gcomp s () ? gfd ? = s () (eq. 14) figure 39. the bode plot of the lc filter, compensator, control to output voltage transfer function, and system loop gain 0 10 20 30 40 50 60 100 1?10 3 frequency (hz) gain (db) -10 -20 -30 -40 -50 -60 1?10 4 1?10 5 1?10 6 compensator lc filter vo/vc loop gain isl6227
19 fn9094.7 may 4, 2009 voltage monitor and protections the converter output is moni tored and protected against extreme overload, short circuit, overvoltage, and undervoltage conditions. a sustained overload on the output sets the pgood low and latches off the offending channel of the chip. the controller operation can be restored by cycling the vcc voltage or toggling both enable (en) pins to low to clear the latch. power good in the soft-start process, the pgood is established after the soft pin voltage is at 1.5v. in normal operation, the pgood window is 100mv below the 0.9v and 135mv higher than 0.9v. the vsen pin has to st ay within this window for pgood to be high. since the vsen pin is used for both feedback and monitoring purposes, the output voltage deviation can be coupled direct ly to the vsen pin by the capacitor in parallel with the voltage divider as shown in figure 4. in order to prevent false pgood drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. the pgood comparator has a built-in 3s filter. pg ood is an open drain output. overcurrent protection in dual switcher application, both pwm controllers use the lower mosfets on-resistance r ds(on), to monitor the current for protection agains t shorted outputs. the sensed current from the isen pin is compared with a current set by a resistor connected from the ocset pin to ground: where, i oc is a desired overcurrent protection threshold and r cs is the value of the current sense resistor connected to the isen pin. the 8a is the offset current added on top of the sensed current from the isen pin for internal circuit biasing. if the lower mosfet current exceeds the overcurrent threshold, a pulse skipping circ uit is activated. the upper mosfet will not be turned on and the lower mosfet keeps conducting as long as the sampled current is higher than the threshold value, limiting the current supplied by the dc voltage source. the current in the lower mosfet will be sampled at the internal 300khz oscillator frequency and monitored. when the sampled current is lower than the oc threshold value, the following ugate pulse will be released and it allows turning on the upper mosfet based on the voltage regulation loop. this kind of operation remains for eight clock cycles after the overcurrent comparator was tripped for the first time. if after the first eight clock cycles the sampled current exceeds the overcurrent threshold again, within a time interval of another eight clock cycles, the overcurrent protection latche s and disables the offending channel. if the overcurrent condition goes away during the first eight clock cycles, normal operation is re stored and the overcurrent circuit resets itself at the end of sixteenth clock cycles; see figure 40. due to the nature of the us ed current sensing technique, and to accommodate a wide range of the r ds(on) variation, the value of the overcurrent threshold should set at about 180% of the nominal load value. if more accurate current protection is desired, a curr ent sense resistor placed in series with the lower mosfet source may be used. the inductor current going through the lower mosfet is sensed and held at 400ns after the upper mosfet is turned off; therefore, the sensed current is very close to its peak value. the inductor peak current ca n be written as equation 16: as seen from equation 16, the inductor peak current changes with the input voltage and the inductor value once an output voltage is selected. after overcurrent protection is activated, there are two ways to bring the offending channel back: (1) both en1 and en2 have to be held low to clear the la tch, (2) to recycle the vcc of the chip, the por will clear the latch. undervoltage protection in the process of operation, if a short circuit occurs, the output voltage will drop quickly. before the overcurrent protection circuit responds, the output voltage will fall out of the required regulation range. the chip comes with undervoltage protection. if a load step is strong enough to pull the output voltage lower than the undervoltage threshold, the offending channel latches off immediately. the undervoltage threshold is 75% of the nominal output voltage. toggling both pins to low, or recycling vcc, will clear the latch and bring the chip back to operation. overvoltage protection should the output voltage incr ease over 115% of the normal value due to the upper mosfet failure, or for other reasons, the overvoltage protection comparator will force the synchronous rectifier gate driver high. this action actively pulls down the output voltage and eventually attempts to blow the battery fuse. as soon as the output voltage is within r set 10.3v i oc r ds on () ? r cs 140 + -------------------------------------- 8 a + -------------------------------------------------------- - = (eq. 15) 3 1 2 shutdown 8 clk il vout ch3 1.0 a m 10.0 i peak v in v o ? () v o ? 2l o f sw v in ? ? ------------------------------------------- - i load + = (eq. 16) isl6227
20 fn9094.7 may 4, 2009 regulation, the ovp comparator is disengaged. the mosfet driver will restore it s normal operation. when the ovp occurs, the pgood will drop to low as well. this ovp scheme provides a ?soft? crowbar function, which helps clamp the voltage overshoot, and does not invert the output voltage when otherwise activated with a continuously high output from lower mosfet driver - a common problem for ovp schemes with a latch. ddr application high throughput double data rate (ddr) memory ics are replacing traditional memory ic s in the latest generation of notebook pcs and in other computing devices. a novel feature associated with th is type of memory are the referencing and data bus termination techniques. these techniques employ a reference voltage, vref, that tracks the center point of vddq and vss voltages, and an additional vtt power source where all terminating resistors are connected. despite the additional power source, the overall memory power consumpt ion is reduced compared to traditional termination. the added power source has a cluster of requirements that should be observed and considered. due to the reduced differential thresholds of ddr memory, the termination power supply voltage, vtt, closely tracks vddq/2 voltage. another very important feature of the termination power supply is the capability to operate at equal efficiency in sourcing and sinking modes. the vtt supply regulates the output voltage with the same degree of precision when current is flowing from the supply to the load, and when the current is diverted back from the load into the power supply. the isl6227 dual channel pwm controller possesses several important enhancements that allow re-configuration for ddr memory applications, and provides all three voltages required in a ddr memory compliant computer. to reconfigure the isl6227 for a complete ddr solution, the ddr pin should be set high permanently to the vcc rail. this activates some functions inside the chip that are specific to ddr memory power needs. in the ddr application presen ted in figure 32, the first controller regulates the v ddq rail to 2.5v. the output voltage is set by external dividers rfb1 and rfb12. the second controller regulates the vtt rail to vddq/2. the ocset2 pin function is now different, and serves as an input that brings vddq/2 voltage, created by the rd1 and rd2 divider, inside the chip, effectively providing a tracking function for the vtt voltage. the pg2 pin function is also different in ddr mode. this pin becomes the output of the buffer, whose input is connected to the center point of the r/r divider from the vddq output by the ocset2 pin. the buffer output voltage serves as a 1.25v reference for the ddr memory chips. current capability of this pin is 10ma (12ma max). for the vtt channel where output is derived from the vddq output, some control and protective functions have been significantly simplified. for example, the overcurrent, and overvoltage, and undervoltage protections for the second channel controller are disabled when the ddr pin is set high. the hysteretic mode of oper ation is also disabled on the vtt channel to allow sinking capability to be independent from the load level. as the vtt channel tracks the vddq/2 voltage, the soft-sta rt function is not required, and the soft2 pin may be left open, in the event both channels are enabled simultaneously. however, if the vtt channel is enabled later than the vddq, the soft2 pin must have a capacitor in place to ensure soft-start. in case of overcurrent or undervoltage caused by short circuit on vtt, the fault current will propagate to the first channel and shut down the converter. the vref voltage will be present even if the vtt is disabled. channel synchronization in ddr applications the presence of two pwm controllers on the same die requires channel synchronization, to reduce inter-channel interference that may caus e the duty factor jitter and increased output ripple. the pwm controller is at great est noise susceptibility when an error signal on the input of the pwm comparator approaches the decision making point. false triggering may occur, causing jitter and affecting the output regulation. a common approach used to synchronize dual channel converters is out-of-phase operation. out-of-phase operation reduces input current ripple and provides a minimum interference for cha nnels that control different voltage levels. when the ddr pin is connected to gnd for dual switcher applications, the channels o perate 180 out-of-phase. when used in a ddr application with cascaded converters (vtt generated from vddq), severa l methods of synchronization are implemented in the isl62 27. in the ddr mode, when the ddr pin is connected to vcc, the channels operate either with 0 phase shift, when the vin pin is connected to the gnd, or with 90 phase shif t if the vin pin is connected to a voltage higher than 4.2v. the following table lists the different synchronization schemes and their usage: ddr pin vin pin synchronization 0 vin pin >4.2v 180 out of phase 1 vin pin voltage <4.2v 0 phase 1 vin pin voltage >4.2v 90 phase shift isl6227
21 fn9094.7 may 4, 2009 application information design procedures general a ceramic decoupling capacitor should be used between the vcc and gnd pin of the chip. there are three major currents drawn from the decoupling capacitor: 1. the quiescent current, supporting the internal logic and normal operation of the ic 2. the gate driver current for the lower mosfets 3. and the current going through the external diodes to the bootstrap capacitor for upper mosfet. in order to reduce the noisy effect of the bootstrap capacitor current to the ic, a small resistor, such as 10 , can be used with the decoupling capacitor to construct a low pass filter for the ic, as shown in figure 41. the soft-start capacitor and the resistor divider setting the output voltage is easy to select as discussed in the ?block diagram? on page 13. selection of the current sense resistor the value of the current sens e resistor determines the gain of the current sensing circuit. it affects the current loop gain and the overcurrent protection setpoint. the voltage drop on the lower mosfet is sensed within 400ns after the upper mosfet is turned off. the current sense pin has a 140 resistor in series with the exte rnal current sensing resistor. the current sense pin can source up to a 260a current while sensing current on the lower mosfet, in such a way that the voltage drop on the current sensing path would be equal to the voltage on the mosfet. i d can be assumed to be the inductor peak current. in a worst case scenario, the high temperature r ds(on) could increase to 150% of the room temperature level. during overload condition, the mosfet drain current i d could be 130% higher than the normal inductor peak. if the inductor has 30% peak-to-peak ripple, i d would equal to 115% of the load current. the design should consider the above factors so that the maximum i sourcing will not saturate to 260a under worst case conditions. to be safe, i sourcing should be less than 100a in norm al operation at room temperature. the formula in the earlier discussion assumes a 75a sourcing current. users can tune the sourcing current of the isen pin to me et the overcurrent protection and the change the current loop gain. the lower the current sensing resistor, the higher gai n of the current loop, which can damp the output lc filter more. a higher value current-sensing resistor will decrease the current sense gain. if the phase node of the converter is very noisy due to poor layout, the sensed current will be contaminated, re sulting in duty cycle jittering by the current loop. in such a case, a bigger current sense resistor can be used to reduce both real and noise current levels. this can help damp the phase node wave form jittering. sometimes, if the phase node is very noisy, a resistor can be put on the isen pin to ground. this resistor together with the r cs can divide the phase node voltage down, seen by the internal current sense amplifier, and reduce noise coupling. sizing the overcurrent setpoint resistor the internal 0.9v reference is buffered to the ocset pin with a voltage follower (refer to the equivalent circuit in figure 42). the current going through the external overcurrent set resistor is se nsed from the ocset pin. this current, divided by 2.9, sets up the overcurrent threshold and compares with the scaled isen pin current going through r cs with an 8a offset. once the sensed current is higher than the threshold value, an oc signal is generated. the first oc signal starts a counter and activates a pulse skipping function. the inductor current will be continuously monitored through the phase node voltage after the first oc trip. as long as the sensed current exceeds the oc threshold value, the following pwm pulse will be skipped. this operation will be the same for 8 switching cycles. another oc occurring between 8 to 16 switching cycles would result in a latch off with both upper and lower drives low. if there is no oc within 8 to 16 switching cycles, normal operation resumes. 10 vcc to boot 5v figure 41. input filtering for the chip i sourcing r cs 140 + () i d r ds on () = (eq. 17) figure 42. equivalent circuit for oc signal generator 0.9v amplifier comparator +2.9 oc oc set r set r ds(on) _ + +33.1 8ua + + phase isen reference i sense 140 r cs 8a + - + - - + isl6227
22 fn9094.7 may 4, 2009 based on the above description and functional block diagram, the oc set resistor can be calculated as equation 18: i oc is the inductor peak curr ent and not the load current. since inductor peak current changes with input voltage, it is better to use an oscilloscope when testing the overcurrent setting point to monitor the inductor current, and to determine when the oc occurs. to get consistent test results on different boards, it is best to keep the mosfet at a fixed temperature. the mosfet will not heat-up when applying a very low frequency and short load pulses with an electronic load to the output. as an example, assume the following: ? the maximum normal operation load current is 1 ? the inductor peak current is 1.15x to 1.3x higher than the load current, depending on the inductor value and the input voltage ?the r ds(on) has a 45% increase at higher temperature i oc should set at least 1.8 to 2 times higher than the maximum load current to avoid nuisance overcurrent trip. selection of the lc filter the duty cycle of a buck converter is a function of the input voltage and output voltage. once an output voltage is fixed, it can be written as equation 19: the switching frequency, f sw , of isl6227 is 300khz. the peak-to-peak ripple current going through the inductor can be written as equation 20: as higher ripple current will result in higher switching loss and higher output voltage ripple, the peak-to-peak current of the inductor is generally designed with a 20% to 40% peak-to-peak ripple of the nominal operation current. based on this assumption, the inductor value can be selected with equation 20. in addition to the mechanical dimension, a shielded ferrite core inductor with a very low dc resistance, dcr, is preferred for less core loss and copper loss. the dc copper loss of the inductor can be estimated by equation 21: the inductor copper loss can be significant in the total system power loss. attention has to be give n to the dcr selection. another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. saturated inductors could result in nuisance oc, or ov trip. output voltage ripple and the tr ansient voltage deviation are factors that have to be taken into consideration when selecting an output capacitor. in addition to high frequency noise related mosfet turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop and esr voltage drop caused by t he ac peak-to-peak current. these two voltages can be represented by equations 22 and 23: these two components constitute a large portion of the total output voltage ripple. several capacitors have to be paralleled in order to reduce the esr and the voltage ripple. if the output of the converter has to support another load with high pulsating current, more capacitors are needed in order to reduce the equivalent esr and suppress the voltage ripple to a tolerable level. to support a load transient that is faster than the switching frequency, more capacitors have to be used to reduce the voltage excursion during load step change. another aspect of the capacitor selection is that the total ac current going through the capacitors has to be less than the rated rms current specified on the capacitors, to prevent the capacitor from over-heating. selection of the input capacitor when the upper mosfet is on , the current in the output inductor will be seen by the input capacitor. even though this current has a triangular shape top, its rms value can be fairly approximated by equation 24: this rms current includes both dc and ac components. since the dc component is the product of duty cycle and load current, the ac component can be approximated by equation 25: ac components will be provided from the input capacitor. the input capacitor has to be able to handle this ripple current without overheating and with tolerable voltage ripple. in addition to the capacitance, a ceramic capacitor is generally used between the drain terminal of the upper r set 10.3v i oc r ds on () r cs 140 + -------------------------------- - 8 a + --------------------------------------------------- = (eq. 18) dv in () v o v in --------- = (eq. 19) i pp v o 1dv in () ? () f sw l o ---------------------------------------- - = (eq. 20) p copper i load dcr 2 = (eq. 21) v c i pp 8c o f sw --------------------- - = (eq. 22) v esr i pp ? esr = (eq. 23) lin rms v in () dv in () *i load = (eq. 24) li nac v in () dv in () dv in () ? 2 () i load = (eq. 25) isl6227
23 fn9094.7 may 4, 2009 mosfet and the source terminal of the lower mosfet, in order to clamp the parasitic voltage ringing at the phase node in switching. choosing mosfets for a notebook battery with a ma ximum voltage of 28v, at least a minimum 30v mosfets should be used. the design has to trade off the gate charge with the r ds(on) of the mosfet: ? for the lower mosfet, before it is turned on, the body diode has been conducting. t he lower mosfet driver will not charge the miller capacitor of this mosfet. ? in the turning off process of the lower mosfet, the load current will shift to the body diode first. the high dv/dt of the phase node voltage will charge the miller capacitor through the lower mosfet driver sinking current path. this results in much less switching loss of the lower mosfets. the duty cycle is often very sm all in high battery voltage applications, and the lower mo sfet will conduct most of the switching cycle; ther efore, the lower the r ds(on) of the lower mosfet, the less the power loss. the gate charge for this mosfet is usually of secondary consideration. the upper mosfet does not have this zero voltage switching condition, and because it conducts for less time compared to the lower mosfet, the switching loss tends to be dominant. priority should be given to the mosfets with less gate charge, so that both the gate driver loss, and switching loss, will be minimized. for the lower mosfet, its powe r loss can be assumed to be the conduction loss only. for the upper mosfet, its conduction loss can be written as equation 27: and its switching loss can be written as equation 28: the peak and valley current of the inductor can be obtained based on the inductor peak-to-peak current and the load current. the turn-on and turn-off time can be estimated with the given gate driver parameters in the ?electrical specifications? table on page 3. for example, if the gate driver turn-on path of mosfet has a typical on-resistance of 4w, its maximum turn-on current is 1.2a with 5v vcc. this current would decay as the gate voltage increased. with the assumption of linear current decay, the turn-on time of the mosfets can be written with equation 29: q gd is used because when the mosfet drain-to-source voltage has fallen to zero, it gets charged. similarly, the turn-off time can be estimated based on the gate charge and the gate drivers sinking current capability. the total power loss of the upper mosfet is the sum of the switching loss and the conduction loss. the temperature rise on the mosfet can be calcul ated based on the thermal impedance given on the datash eet of the mosfet. if the temperature rise is too much, a different mosfet package size, layout copper size, and other options have to be considered to keep the mosfet cool. the temperature rise can be calculated by equation 30: the mosfet gate driver loss c an be calculated with the total gate charge and the driver voltage v cc . the lower mosfet only charges the miller capacitor at turn-off. based on equation 31, t he system efficiency can be estimated by the designer. confining the negative phase node voltage swing with schottky diode at each switching cycle, the body diode of the lower mosfet will conduct before the mosfet is turned on, as the inductor current is flowing to the output capacitor. this will result in a negative voltage on the phase node. the higher the load current, the lower this negative voltage. this voltage will ring back less negative when the lower mosfet is turned on. a total 400ns period is given to the current sample-and-hold circuit on the isen pin to sense the current going through the lower mosfet after the upper mosfet turns off. an excessive negative voltage on the lower mosfet will be treated as overcurrent. in order to confine this voltage, a schottky diode can be used in parallel with the lower mosfet for high load current applications. pcb layout parasitics should be minimized in order to reduce the negative ringing of phase voltage. the second concern for the phase node voltage going into negative is that the boot st rap capacitor between the boot and phase pin could get be charge d higher than vcc voltage, exceeding the 6.5v absolute maximum voltage between boot and phase when the phase node voltage became negative. a resistor can be placed between the cathode of the boot strap diode and boot pin to increase the charging time constant of the boot cap. this resistor will not affect the turn-on and off of the upper mosfet. schottky diode can reduce the reverse recovery of the lower mosfet when transition from freewheeling to blocking, therefore, it is generally g ood practice to have a schottky diode closely parallel with the lower mosfet. b340la, from diodes, inc.?, can be used as the external schottky diode. p lower v in () 1dv in () ? () i load r 2 ds on () lower (eq. 26) p uppercond v in () dv in () i load r 2 ds on () upper = (eq. 27) p uppersw v in () v in i vally t on f sw 2 ------------------------------------------- - v in i peak t off f sw 2 -------------------------------------------- - + = (eq. 28) t on 2q gd i driver ---------------- - = (eq. 29) t rise p ja totalpower loss = (eq. 30) p driver v cc q gs f sw = (eq. 31) isl6227
24 fn9094.7 may 4, 2009 tuning the turn-on of upper mosfet the turn-on speed of the uppe r mosfet can be adjusted by the resistor connecting the boot cap to the boot pin of the chip. this resistor can confine the voltage ringing on the boot capacitor from coupling to the boot pin. this resistor slows down only the turn-on of the upper mosfet. if the upper mosfet is turned on very fast, it could result in a very high dv/dt on the phase node, which could couple into the lower mosfet gate through the miller capacitor, causing momentous shoot-th rough. this phenomenon, together with the reverse recovery of the body diode of the lower mosfet, can over-shoot the phase node voltage to beyond the voltage rating of the mosfet. however, a bigger resistor will slow the turn-on of the mosfet too much and lower the efficiency. trade-offs need to be made in choosing a suitable resistor value. system loop gain and stability the system loop gain is a product of three transfer functions: 1. the transfer function from the output voltage to the feedback point, 2. the transfer function of the internal compensation circuit from the feedback point to the error amplifier output voltage, 3. and the transfer function from the error amplifier output to the converter output voltage. these transfer functions are wri tten in a closed form in the ?theory of operation? on page 14. the external capacitor, in parallel with the upper resistor of the resistor divider, c z , can be used to tune the loop gain and phase margin. other component parameters, such as the inductor value, can be changed for a wider cross-over frequency of the system loop gain. a body plot of the loop gain transfer function with a 45 phase margin (a 60 phase margin is better) is desirable to cover component parameter variations. testing the overvoltage on buck converters for synchronous buck converters, if an active source is used to raise the output voltage for the overvoltage protection test, the buck converter will behave like a boost converter and dump energy from the external source to the input. the overvoltage test can be done on isl6227 by connecting the vsen pin to an external voltag e source or signal generator through a diode. when the external voltage, or signal generator voltage, is tuned to a higher level than the overvoltage threshold (the lowe r mosfet will be on), it indicates the overvoltage protection works. this kind of overvoltage protection does not require an external schottky in parallel with the output capacitor. layout considerations power and signal layer placement on the pcb as a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. for example, prospective layer arrangement on a 4 layer board is shown below: 1. top layer: isl6227 signal lines 2. signal ground 3. power layers: power ground 4. bottom layer: power mosfet, inductors and other power traces it is a good engineering practice to separate the power voltage and current flowing path from the control and logic level signal path. the controller ic will stay on the signal layer, which is isolated by the signal ground to the power signal traces. component placement the control pins of the two-channel isl6227 are located symmetrically on two sides of the ic; it is desirable to arrange the two channels symmetrically around the ic. the power mosfet should be close to the ic so that the gate drive signal, the lgat ex, ugatex, phasex, bootx, and isenx traces can be short. place the components in such a way that the area under the isl6227 has fewer noise traces with high dv/dt and di/dt, such as gate signals and phase node signals. signal ground and power ground connection at minimum, a reasonably lar ge area of copper, which will shield other noise couplings through the ic, could be used as signal ground beneath the isl6227. the best tie-point between the signal ground and the power ground is at the negative side of the output ca pacitor on each channel, where there is less noise. noisy traces beneath the isl6227 are not recommended. gnd and vcc at least one high quality ceramic decoupling cap should be used across these two pins. a via can tie pin 1 to signal ground. since pin 1 and pin 28 are close together, the decoupling cap can be put close to the ic. lgate1 and lgate2 these are the gate drive signals for the bottom mosfets of the buck converter. the signal going through these traces have both high dv/dt and high di/dt, with high peak charging and discharging current. these two traces should be short, wide, and away from other traces. there should be no other weak signal traces in parallel with these traces on any layer. pgnd1 and pgnd2 each pin should be laid out to the negative side of the relevant output capacitor with separate traces.the negative side of the output capacitor must be close to the source node of the bottom mosfet. these traces are the return path of lgate1 and lgate2. isl6227
25 fn9094.7 may 4, 2009 phase1 and phase2 these traces should be short, and positioned away from other weak signal traces. the phase no de has a very high dv/dt with a voltage swing from the input voltage to ground. no trace should be in parallel with these tr aces. these traces are also the return path for ugate1 and ugate2. connect these pins to the respective converter?s upper mosfet source. pin 5 and pin 24, the ugate1 and ugate2 these pins have a square shape waveform with high dv/dt. it provides the gate drive current to charge and discharge the top mosfet with high di/dt. this trace should wide, short, and away from other traces similar to the lgatex. boot1 and boot2 these pins di/dt are as high as that of the ugatex; therefore, the traces shou ld be as short as possible. isen1 and isen2 the isen trace should be a separate trace, and independently go to the drain terminal of the lower mosfet. the current sense resistor should be close to isen pin. the loop formed by the bottom mosfet, output inductor, and output capacitor, should be very small. the source of the bottom mosfet should tie to the negative side of the output capacitor in order for t he current sense pin to get the voltage drop on the r ds(on) . en1 and en2 these pins stay high in enable mode and low in idle mode and are relatively robust. enable signals should refer to the signal ground. vout1 and vout2 these pins connect either to the output voltage or to the signal ground. they are signal lines and should be kept away from noisy lines. vsen1 and vsen2 there is usually a resistor divider connecting the output voltage to this pin. the input impedance of these two pins is high because they are the input to the amplifiers. the correct layout should bring the output voltage from the regulation point to the sen pin with kelvin traces. build the resistor divider close to the pin so that the high impedance trace is shorter. ocset1 and ocset2 in dual switcher mode operatio n, the overcurrent set resistor should be put close to this pin. in ddr mode operation, the voltage divider, which divides the vdqq voltage in half, should be put very close to this pin. the other side of the oc set resistor should connect to signal ground. soft1 and soft2 the soft-start capacitors should be laid out close to this pin. the other side of the soft-start cap should tie to signal ground. pg1 and pg2/ref for dual switcher operations, these two lines are less noise sensitive. for ddr applications, a capacitor should be placed to the pg2/ref pin. ddr this pin should connect to vcc in ddr applications, and to signal ground in dual switcher applications. vin this pin connects to battery volt age, and is less noise sensitive. copper size for the phase node big coppers on both sides of the phase node introduce parasitic capacitance. the ca pacitance of phase should be kept very low to minimize ringi ng. if ringing is excessive, it could easily affect current sample information. it would be best to limit the size of the phase node copper in strict accordance with the current and thermal management of the application. identify the power and signal ground the input and output capacitors of the converters, the source terminals of the bottom switching mosfet pgnd1, and pgnd2, should be closely c onnected to the power ground. the other components should connect to signal ground. signal and power ground are ti ed together at the negative terminal of the output capacitors. decoupling capacitor for switching mosfet it is recommended that ceramic caps be used closely connected to the drain side of the upper mosfet, and the source of the lower mosfet. this capacitor reduces the noise and the power loss of the mosfet. refer to figure 43 for the power component placement. . in - + v - + l o in - + o - + l o v o - + output cap inductor l o si4816dy 1 2 3 4 8 7 6 5 + vin - figure 43. a good example power component replacement. it shows the negative of input and output capacitor and source of the mosfet are tied at one point. isl6227
26 fn9094.7 may 4, 2009 isl6227 package outline drawing l28.5x5 28 lead quad flat no-lead plastic package rev 2, 10/07 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 28x 0.55 0.10 4 a 28x 0.25 m 0.10 c b 14 8 4x 0.50 24x 3.0 6 pin #1 index area 3 .10 0 . 15 0 . 90 0.1 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 10) ( 4. 65 typ ) ( 24x 0 . 50) (28x 0 . 25 ) ( 28x 0 . 75) 15 22 21 7 1 28 + 0.05 - 0.07
27 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9094.7 may 4, 2009 isl6227 isl6227 shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual in- dex feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dam- bar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. c onverted millimeter dimensions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m28.15 28 lead shrink small outline plastic package (0.150? wide body) symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - a2 - 0.061 - 1.54 - b 0.008 0.012 0.20 0.30 9 c 0.007 0.010 0.18 0.25 - d 0.386 0.394 9.81 10.00 3 e 0.150 0.157 3.81 3.98 4 e 0.025 bsc 0.635 bsc - h 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 l 0.016 0.050 0.41 1.27 6 n28 287 0 8 0 8 - rev. 1 6/04

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